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ltc2635 1 2635fb block diagram description quad 12-/10-/8-bit i 2 c v out dacs with 10ppm/c reference the ltc ? 2635 is a family of quad 12-, 10-, and 8-bit voltage-output dacs with an integrated, high-accuracy, low-drift reference in a 16-pin qfn or a 10-lead msop package. it has rail-to-rail output buffers and is guaran- teed monotonic. the ltc2635-l has a full-scale output of 2.5v, and operates from a single 2.7v to 5.5v supply. the ltc2635-h has a full-scale output of 4.096v, and operates from a 4.5v to 5.5v supply. each dac can also operate with an external reference, which sets the full- scale output to the external reference voltage. these dacs communicate via a 2-wire i 2 c-compatible serial interface. the ltc2635 operates in both the st andard mode (clock rate of 100khz) and the fast mode (clock rate of 400khz). the ltc2635 incorporates a power-on reset circuit. options are available for reset to zero-scale, reset to mid-scale in internal reference mode, reset to mid-scale in external reference mode, or reset with all dac outputs in a high-impedance state after power-up. integral nonlinerity features applications n integrated precision reference 2.5v full-scale 10ppm/c (ltc2635-l) 4.096v full-scale 10ppm/c (ltc2635-h) n maximum inl error: 2.5 lsb (ltc2635-12) n power-on-reset to zero-scale/mid-scale/hi-z n low noise: 0.75mv p-p 0.1hz to 200khz n guaranteed monotonic over C40c to 125c automotive temperature range n selectable internal or external reference n 2.7v to 5.5v supply range (ltc2635-l) n ultralow crosstalk between dacs (3nvs) n low power: 0.6ma at 3v n double-buffered data latches n small 16-pin 3mm 3mm qfn and 10-lead msop packages n mobile communications n process control and industrial automation n power supply margining n portable equipment n automotive register register register register dac a v outa (reflo) ( ldac ) ca0 (ca1) (ca2) ( ) qfn package only gndv outb v ref dac d register register register register dac b dac c v ref v outd ref v cc v ref v outc switch internal reference i 2 c interface decode i 2 c address decode power-on reset scl sda 2635 bd l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5396245, 5859606, 6891433, 6937178, 7414561. code 0 inl (lsb) 21 0 C1C2 1024 3072 2635 ta01 4095 2048 v cc = 3v internal ref. downloaded from: http:///
ltc2635 2 2635fb pin configuration absolute maximum ratings supply voltage (v cc ) ................................... C0.3v to 6v scl, sda, reflo, ldac .............................. C0.3v to 6v v outa-d , ca0, ca1, ca2 ...... C0.3v to min (v cc + 0.3v, 6v) ref .................................... C0.3v to min (v cc + 0.3v, 6v) operating temperature range ltc2635c ................................................ 0c to 70c ltc2635h (note 3) ............................ C40c to 125c (notes 1, 2) maximum junction temperature .......................... 150c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) ms package ...................................................... 300c 16 15 14 13 5 6 7 8 top view 17 gnd ud package 16-lead (3mm 3mm) plastic qfn 9 10 11 12 4 3 2 1 v outa v outb ldac ca0 v outd v outc refca1 v cc dncgnd reflo scl dnc ca2 sda t jmax = 150c, ja = 68c/w exposed pad (pin 17) is gnd, must be soldered to pcb 12 3 4 5 v cc v outa v outb ca0scl 109 8 7 6 gndv outd v outc refsda top view 11 gnd mse package 10-lead plastic msop t jmax = 150c, ja = 35c/w exposed pad (pin 11) is gnd, must be soldered to pcb downloaded from: http:///
ltc2635 3 2635fb order information ltc2635 c ud ?l z 12 #tr pbf lead free designator pbf = lead free tape and reel tr = 2,500-piece tape and reel resolution 12 = 12-bit 10 = 10-bit 8 = 8-bit power-0n reset mi = reset to mid-scale in internal reference mode mx = reset to mid-scale in external reference mode (lmx only) mo = reset to mid-scale in internal reference mode, dac outputs hi-z (lmo only) z = reset to zero-scale in internal reference mode full-scale voltage, internal reference mode l = 2.5v h = 4.096v package type ud = 16-pin qfn mse = 10-lead msop temperature grade c = commercial temperature range (0c to 70c) h = automotive temperature range (C40c to 125c) product part number consult ltc marketing for information on non-standard lead based inish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speciications, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc2635 4 2635fb product selection guide part number part marking* vfs with internal reference power-on reset to code power-on reference mode resolution v cc maximum inl qfn msop ltc2635-lmi12 ltc2635-lmi10 ltc2635-lmi8 ldzb ldzj ldzr ltdzy ltfbg ltfbp 2.5v (4095/4096) 2.5v (1023/1024) 2.5v (255/256) mid-scale mid-scale mid-scale internal internal internal 12-bit 10-bit 8-bit 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2635-lmx12 ltc2635-lmx10 ltc2635-lmx8 ldyz ldzh ldzq ltdzx ltfbf ltfbn 2.5v (4095/4096) 2.5v (1023/1024) 2.5v (255/256) mid-scale mid-scale mid-scale external external external 12-bit 10-bit 8-bit 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2635-lz12 ltc2635-lz10 ltc2635-lz8 ldyy ldzg ldzp ltdzw ltfbd ltfbm 2.5v (4095/4096) 2.5v (1023/1024) 2.5v (255/256) zero-scale zero-scale zero-scale internal internal internal 12-bit 10-bit 8-bit 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2635-lmo12** ltc2635-lmo10** ltc2635-lmo8** lfbt lfbv lfbw ltfbx ltfby ltfbz 2.5v (4095/4096) 2.5v (1023/1024) 2.5v (255/256) high impedance high impedance high impedance internal internal internal 12-bit 10-bit 8-bit 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2635-hmi12 ltc2635-hmi10 ltc2635-hmi8 ldzf ldzn ldzv ltfbc ltfbk ltfbs 4.096v (4095/4096) 4.096v (1023/1024) 4.096v (255/256) mid-scale mid-scale mid-scale internal internal internal 12-bit 10-bit 8-bit 4.5v to 5.5v 4.5v to 5.5v 4.5v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2635-hz12 ltc2635-hz10 ltc2635-hz8 ldzc ldzk ldzs ltdzz ltfbh ltfbq 4.096v (4095/4096) 4.096v (1023/1024) 4.096v (255/256) zero-scale zero-scale zero-scale internal internal internal 12-bit 10-bit 8-bit 4.5v to 5.5v 4.5v to 5.5v 4.5v to 5.5v 2.5lsb 1lsb 0.5lsb *above options are available in a 16-pin qfn package (ltc2635xud) or 10-lead msop package (ltc2635xmse). **contact linear technology for other hi-z options. downloaded from: http:///
ltc2635 5 2635fb electrical characteristics the l denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise speci?ed. ltc2635-lmi12/-lmi10/-lmi8/-lmx12/-lmx10/-lmx8/-lz1 2/-lz10/-lz8/-lmo12/-lmo10/-lm08 (v fs = 2.5v) symbol parameter conditions ltc2635-8 ltc2635-10 ltc2635-12 units min typ max min typ max min typ max dc performance resolution l 8 10 12 bits monotonicity v cc = 3v, internal ref. (note 4) l 8 10 12 bits dnl differential nonlinearity v cc = 3v, internal ref. (note 4) l 0.5 0.5 1 lsb inl integral nonlinearity v cc = 3v, internal ref. (note 4) l 0.05 0.5 0.2 1 1 2.5 lsb zse zero-scale error v cc = 3v, internal ref., code=0 l 0.5 5 0.5 5 0.5 5 mv v os offset error v cc = 3v, internal ref. (note 5) l 0.5 5 0.5 5 0.5 5 mv v ostc v os temperature coefficient v cc = 3v, internal ref. 10 10 10 v/c ge gain error v cc = 3v, internal ref. l 0.2 0.8 0.2 0.8 0.2 0.8 %fsr ge tc gain temperature coefficient v cc = 3v, internal ref. (note 10) c-grade h-grade 10 10 1010 10 10 ppm/c ppm/c load regulation internal ref., mid-scale, v cc = 3v 10%, C5ma i out 5ma v cc = 5v10%, C10ma i out 10ma l l 0.009 0.009 0.016 0.016 0.035 0.035 0.064 0.064 0.14 0.14 0.256 0.256 lsb/ma lsb/ma r out dc output impedance internal ref., mid-scale, v cc = 3v 10%, C5ma i out 5ma v cc = 5v10%, C10ma i out 10ma l l 0.09 0.09 0.156 0.156 0.09 0.09 0.156 0.156 0.09 0.09 0.156 0.156 symbol parameter conditions min typ max units v out dac output span external reference internal reference 0 to v ref 0 to 2.5 v v psr power supply rejection v cc = 3v 10% or 5v 10% C80 db i sc short circuit output current (note 6) sinking sourcing v fs = v cc = 5.5v zero-scale; v out shorted to v cc full-scale; v out shorted to gnd l l 27 C28 48 C48 ma ma dac i sd dac output current in high impedance mode sinking sourcing mo options only l l 0.05 C0.001 2 C0.1 a a power supplyv cc positive supply voltage for specified performance l 2.7 5.5 v i cc supply current (note 7) v cc = 3v, v ref = 2.5v, external reference v cc = 3v, internal reference v cc = 5v v ref = 2.5v, external reference v cc = 5v, internal reference l l l l 0.5 0.6 0.6 0.7 0.7 0.8 0.8 0.9 ma ma ma ma i sd supply current in power-down mode (note 7) v cc = 5v, c-grade v cc = 5v, h-grade l l 1 1 20 30 a a downloaded from: http:///
ltc2635 6 2635fb electrical characteristics the l denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise speci?ed. ltc2635-lmi12/-lmi10/-lmi8/-lmx12/-lmx10/-lmx8/-lz1 2/-lz10/-lz8/-lmo12/-lmo10/-lm08 (v fs = 2.5v) symbol parameter conditions min typ max units reference input input voltage range l 1 v cc v resistance l 120 160 200 k capacitance 14 pf i ref reference current, power-down mode dac powered down l 0.005 1.5 a reference output output voltage l 1.24 1.25 1.26 v reference temperature coefficient 10 ppm/c output impedance 0.5 k capacitive load driving 10 f short circuit current v cc = 5.5v, ref shorted to gnd 2.5 ma digital i/ov il low level input voltage (sda and scl) (note 14) l C0.5 0.3v cc v v ih high level input voltage (sda and scl) (note 11) l 0.7v cc v v il(can) low level input voltage on ca n ( n = 0, 1,2) see test circuit 1 l 0.15v cc v v ih(can) high level input voltage on ca n ( n = 0, 1,2) see test circuit 1 l 0.85v cc v r inh resistance from ca n ( n = 0, 1,2) to v cc to set ca n = v cc see test circuit 2 l 10 k r inl resistance from ca n ( n = 0, 1,2) to gnd to set ca n = gnd see test circuit 2 l 10 k r inf resistance from ca n ( n = 0, 1,2) to v cc or gnd to set ca n = float see test circuit 2 l 2 m v ol low level output voltage sink current = 3ma l 0 0.4 v t of output fall time v o = v ih(min) to v o = v il(max) , c b = 10pf to 400pf (note 12) l 20 + 0.1c b 250 ns t sp pulse width of spikes suppressed by input filter l 0 50 ns i in input leakage 0.1v cc v in 0.9v cc l 1 a c in i/o pin capacitance (note 8) l 10 pf c b capacitive load for each bus line l 400 pf c can external capacitive load on address pin ca n ( n = 0, 1,2) l 10 pf downloaded from: http:///
ltc2635 7 2635fb electrical characteristics the l denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise speci?ed. ltc2635-lmi12/-lmi10/-lmi8/-lmx12/-lmx10/-lmx8/-lz1 2/-lz10/-lz8/-lmo12/-lmo10/-lm08 (v fs = 2.5v) symbol parameter conditions min typ max units ac performancet s settling time v cc = 3v (note 9) 0.39% (1lsb at 8 bits) 0.098% (1lsb at 10 bits) 0.024% (1lsb at 12 bits) 3.5 4.1 4.4 s s s voltage output slew rate 1 v/s capacitive load driving 500 pf glitch impulse at mid-scale transition 2.1 nv s dac-to-dac crosstalk 1 dac held at fs, 1 dac switched 0 to fs 2.6 nv s multiplying bandwidth external reference 320 khz e n output voltage noise density at f = 1khz, external reference at f = 10khz, external reference at f = 1khz, internal reference at f = 10khz, internal reference 180 160 200 180 nv/ hz nv/ hz nv/ hz nv/ hz output voltage noise 0.1hz to 10hz, external reference 0.1hz to 10hz, internal reference 0.1hz to 200khz, external reference 0.1hz to 200khz, internal reference c ref = 0.1f 35 40 680 730 v p-p v p-p v p-p v p-p timing characteristics the l denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. v cc = 2.7v to 5.5v. (see figure 1) (note 13) ltc2635-lmi12/-lmi10/-lmi8/-lmx12/-lmx10/-lmx8/-lz1 2/-lz10/-lz8/-lmo12/-lmo10/-lm08 (v fs = 2.5v) symbol parameter conditions min typ max units f scl scl clock frequency l 0 400 khz t hd(sta) hold time (repeated) start condition l 0.6 s t low low period of the scl clock pin l 1.3 s t high high period of the scl clock pin l 0.6 s t su(sta) set-up time for a repeated start condition l 0.6 s t hd(dat) data hold time l 0 0.9 s t su(dat) data set-up time l 100 ns t r rise time of both sda and scl signals (note 12) l 20 + 0.1c b 300 ns t f fall time of both sda and scl signals (note 12) l 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s t buf bus free time between a stop and start condition l 1.3 s t 1 falling edge of 9 th clock of the 3 rd input byte to ldac high or low transition l 400 ns t 2 ldac low pulse width l 20 ns downloaded from: http:///
ltc2635 8 2635fb electrical characteristics the l denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise speci?ed. ltc2635-hmi12/-hmi10/-hmi8/-hz12/-hz10/-hz8 (v fs = 4.096v) symbol parameter conditions ltc2635-8 ltc2635-10 ltc2635-12 units min typ max min typ max min typ max dc performance resolution l 8 10 12 bits monotonicity v cc = 5v, internal ref. (note 4) l 8 10 12 bits dnl differential nonlinearity v cc = 5v, internal ref. (note 4) l 0.5 0.5 1 lsb inl integral nonlinearity v cc = 5v, internal ref. (note 4) l 0.05 0.5 0.2 1 1 2.5 lsb zse zero-scale error v cc = 5v, internal ref., code=0 l 0.5 5 0.5 5 0.5 5 mv v os offset error v cc = 5v, internal ref. (note 5) l 0.5 5 0.5 5 0.5 5 mv v ostc v os temperature coefficient v cc = 5v, internal reference 10 10 10 v/c ge gain error v cc = 5v, internal reference l 0.2 0.8 0.2 0.8 0.2 0.8 %fsr ge tc gain temperature coefficient v cc = 5v, internal ref. (note 10) c-grade h-grade 10 10 10 10 10 10 ppm/c ppm/c load regulation internal reference, mid-scale, v cc = 5v 10%, C10ma i out 10ma l 0.006 0.01 0.022 0.04 0.09 0.16 lsb/ma r out dc output internal reference, mid-scale, v cc = 5v 10%, C10ma i out 10ma l 0.09 0.156 0.09 0.156 0.09 0.156 symbol parameter conditions min typ max units v out dac output span external reference internal reference 0 to v ref 0 to 4.096 v v psr power supply rejection v cc = 5v10% C80 db i sc short circuit output current (note 6) sinking sourcing v fs = v cc = 5.5v zero-scale; v out shorted to v cc full-scale; v out shorted to gnd l l 27 C28 48 C48 ma ma power supplyv cc positive supply voltage for specified performance l 4.5 5.5 v i cc supply current (note 7) v cc = 3v, v ref = 4.096v, external reference v cc = 3v, internal reference l l 0.6 0.7 0.8 0.9 ma ma i sd supply current in power-down mode (note 7) v cc = 5v, c-grade v cc = 5v, h-grade l l 1 1 20 30 a a downloaded from: http:///
ltc2635 9 2635fb symbol parameter conditions min typ max units reference input input voltage range l 1 v cc v resistance l 120 160 200 k capacitance 14 pf i ref reference current, power-down mode dac powered down l 0.005 1.5 a reference output output voltage l 2.032 2.048 2.064 v reference temperature coefficient 10 ppm/c output impedance 0.5 k capacitive load driving 10 f short circuit current v cc = 5.5v, ref shorted to gnd 4 ma digital i/ov il low level input voltage (sda and scl) (note 14) l C0.5 0.3v cc v v ih high level input voltage (sda and scl) (note 11) l 0.7v cc v v il(can) low level input voltage on ca n ( n = 0, 1,2) see test circuit 1 l 0.15v cc v v ih(can) high level input voltage on ca n ( n = 0, 1,2) see test circuit 1 l 0.85v cc v r inh resistance from ca n ( n = 0, 1,2) to v cc to set ca n = v cc see test circuit 2 l 10 k r inl resistance from ca n ( n = 0, 1,2) to gnd to set ca n = gnd see test circuit 2 l 10 k r inf resistance from ca n ( n = 0, 1,2) to v cc or gnd to set ca n = float see test circuit 2 l 2 m v ol low level output voltage sink current = 3ma l 0 0.4 v t of output fall time v o = v ih(min) to v o = v il(max) , c b = 10pf to 400pf (note 12) l 20 + 0.1c b 250 ns t sp pulse width of spikes suppressed by input filter l 0 50 ns i in input leakage 0.1v cc v in 0.9v cc l 1 a c in i/o pin capacitance (note 8) l 10 pf c b capacitive load for each bus line l 400 pf c can external capacitive load on address pin ca n ( n =0, 1,2) l 10 pf electrical characteristics the l denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise speci?ed. ltc2635-hmi12/-hmi10/-hmi8/-hz12/-hz10/-hz8 (v fs = 4.096v) downloaded from: http:///
ltc2635 10 2635fb electrical characteristics the l denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise speci?ed. ltc2635-hmi12/-hmi10/-hmi8/-hz12/-hz10/-hz8 (v fs = 4.096v) symbol parameter conditions min typ max units ac performancet s settling time v cc = 5v (note 9) 0.39% (1lsb at 8 bits) 0.098% (1lsb at 10 bits) 0.024% (1lsb at 12 bits) 3.9 4.3 5 s s s voltage output slew rate 1 v/s capacitive load driving 500 pf glitch impulse at mid-scale transition 3 nv s dac-to-dac crosstalk 1 dac held at fs, 1 dac switched 0 to fs 3 nv s multiplying bandwidth external reference 320 khz e n output voltage noise density at f = 1khz, external reference at f = 10khz, external reference at f = 1khz, internal reference at f = 10khz, internal reference 180 160 250 230 nv/ hz nv/ hz nv/ hz nv/ hz output voltage noise 0.1hz to 10hz, external reference 0.1hz to 10hz, internal reference 0.1hz to 200khz, external reference 0.1hz to 200khz, internal reference c ref = 0.1f 35 50 680 750 v p-p v p-p v p-p v p-p timing characteristics the l denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. v cc = 4.5v to 5.5v. (see figure 1) (note 13) ltc2635-hmi12/-hmi10/-hmi8/-hz12/-hz10/-hz8 (v fs = 4.096v) symbol parameter conditions min typ max units f scl scl clock frequency l 0 400 khz t hd(sta) hold time (repeated) start condition l 0.6 s t low low period of the scl clock pin l 1.3 s t high high period of the scl clock pin l 0.6 s t su(sta) set-up time for a repeated start condition l 0.6 s t hd(dat) data hold time l 0 0.9 s t su(dat) data set-up time l 100 ns t r rise time of both sda and scl signals (note 12) l 20+0.1c b 300 ns t f fall time of both sda and scl signals (note 12) l 20+0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s t buf bus free time between a stop and start condition l 1.3 s t 1 falling edge of 9 th clock of the 3 rd input byte to ldac high or low transition l 400 ns t 2 ldac low pulse width l 20 ns downloaded from: http:///
ltc2635 11 2635fb note 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. all voltages are with respect to gnd. note 3. high temperatures degrade operating lifetimes. operating lifetime is derated at temperatures greater than 105c. operating at temperatures above 90c and with v cc > 4v requires v cc slew rates to be no greater than 73mv/ms. note 4. linearity and monotonicity are defined from code k l to code 2 n C 1, where n is the resolution and k l is given by k l = 0.016 (2 n / v fs ), rounded to the nearest whole code. for v fs = 2.5v and n = 12, k l = 26 and linearity is defined from code 26 to code 4,095. for v fs = 4.096v and n = 12, k l = 16 and linearity is defined from code 16 to code 4,095. note 5. inferred from measurement at code 16 (ltc2635-12), code 4 (ltc2635-10) or code 1 (ltc2635-8), and at full-scale. note 6. this ic includes current limiting that is intended to protect the device during momentary overload conditions. junction temperature can exceed the rated maximum during current limiting. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 7. digital inputs at 0v or v cc . note 8. guaranteed by design and not production tested. note 9. internal reference mode. dac is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. load is 2k in parallel with 100pf to gnd. note 10. temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range.note 11. maximum v ih = v cc(max) + 0.5v. note 12. c b = capacitance of one bus line in pf. note 13. all values refer to v ih = v ih(min) and v il = v il(max) levels. note 14. minimum v il exceeds the absolute maximum rating. this condition wont damage the ic, but could degrade performance. electrical characteristics downloaded from: http:///
ltc2635 12 2635fb typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature dnl vs temperature reference output voltage vs temperature settling to 1 lsb rising settling to 1 lsb falling t a = 25c, unless otherwise noted. code 0 inl (lsb) 1.00.5 0 C0.5C1.0 1024 3072 2635 g01 4095 2048 v cc = 3v code 0 dnl (lsb) 1.00.5 0 C0.5C1.0 1024 3072 2635 g02 4095 2048 v cc = 3v temperature (c) C50 inl (lsb) 1.00.5 0 C0.5C1.0 C25 125 100 75 50 25 2635 g03 150 0 v cc = 3v inl (pos) inl (neg) temperature (c) C50 dnl (lsb) 1.00.5 0 C0.5C1.0 C25 125 100 75 50 25 2635 g04 150 0 v cc = 3v dnl (pos) dnl (neg) temperature (c) C50 v ref (v) 1.2601.255 1.250 1.245 1.240 C25 125 100 75 50 25 2635 g05 150 0 v cc = 3v ltc2635-l12 (internal reference, v fs = 2.5v) 2s/div v out 1 lsb/div scl 5v/div 2635 g06 3.3s 9th clock of 3rd data byte 1/4 scale to 3/4 scale step v cc = 3v, v fs = 2.5v r l = 2k, c l = 100pf average of 256 events 2s/div v out 1 lsb/div scl 5v/div 2635 g07 3/4 scale to 1/4 scale step v cc = 3v, v fs = 2.5v r l = 2k, c l = 100pf average of 256 events 4.4s 9th clock of 3rd data byte downloaded from: http:///
ltc2635 13 2635fb typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature dnl vs temperature reference output voltage vs temperature settling to 1 lsb rising settling to 1 lsb falling ltc2635-h12 (internal reference, v fs = 4.096v) code 0 inl (lsb) 1.00.5 0 C0.5C1.0 1024 3072 2635 g08 4095 2048 v cc = 5v code 0 dnl (lsb) 1.00.5 0 C0.5C1.0 1024 3072 2635 g09 4095 2048 v cc = 5v temperature (c) C50 inl (lsb) 1.00.5 0 C0.5C1.0 C25 125 100 75 50 25 2635 g10 150 0 v cc = 5v inl (pos) inl (neg) temperature (c) C50 dnl (lsb) 1.00.5 0 C0.5C1.0 C25 125 100 75 50 25 2635 g11 150 0 v cc = 5v dnl (pos) dnl (neg) temperature (c) C50 v ref (v) 2.0682.058 2.048 2.038 2.028 C25 125 100 75 50 25 2635 g12 150 0 v cc = 5v t a = 25c, unless otherwise noted. 2s/div v out 1 lsb/div scl 5v/div 2635 g13 1/4 scale to 3/4 scale step v cc = 5v, v fs = 4.095v r l = 2k, c l = 100pf average of 256 events 3.9s 9th clock of 3rd data byte 2s/div v out 1 lsb/div scl 5v/div 2635 g14 3/4 scale to 1/4 scale step v cc = 5v, v fs = 4.095v r l = 2k, c l = 100pf average of 256 events 5s 9th clock of 3rd data byte downloaded from: http:///
ltc2635 14 2635fb typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) ltc2635-10 integral nonlinearity (inl) differential nonlinearity (dnl) ltc2635-8 load regulation current limiting ltc2635 offset error vs temperature t a = 25c, unless otherwise noted. code 0 inl (lsb) 1.00.5 0 C0.5C1.0 256 768 2635 g15 1023 512 v cc = 3v v fs = 2.5v internal ref code 0 dnl (lsb) 1.00.5 0 C0.5C1.0 256 768 2635 g16 1023 512 v cc = 3v v fs = 2.5v internal ref code 0 inl (lsb) 0.500.25 0 C0.25C0.50 64 192 2635 g17 255 128 v cc = 3v v fs = 2.5v internal ref code 0 dnl (lsb) 0.500.25 0 C0.25C0.50 64 192 2635 g18 255 128 v cc = 3v v fs = 2.5v internal ref i out (ma) C30 v out (mv) 10 86 4 2 C6 C4 C2 0 C8 C10 C20 20 10 0 2635 g19 30 C10 v cc = 5v (ltc2635-h) v cc = 5v (ltc2635-l) v cc = 3v (ltc2635-l) internal ref. code = mid-scale i out (ma) C30 v out (v) 0.200.15 0.10 0.05 C0.15 C0.01 C0.05 0 C0.20 C20 20 10 0 2635 g20 30 C10 v cc = 5v (ltc2635-h) v cc = 5v (ltc2635-l) v cc = 3v (ltc2635-l) internal ref. code = mid-scale temperature (c) C50 offset error (mv) 32 1 0 C1C2 C3 C25 125 100 75 50 25 2635 g21 150 0 downloaded from: http:///
ltc2635 15 2635fb typical performance characteristics large-signal response mid-scale glitch impulse power-on reset gli tch headroom at rails vs output current exiting power-down to mid-scale power-on reset to mid-scale supply current vs logic voltage ltc2635 t a = 25c, unless otherwise noted. 2s/div v out 0.5v/div 2635 g22 v fs = v cc = 5v 1/4 scale to 3/4 scale 200s/div v out 5mv/div v cc 2v/div 2635 g24 ltc2635-l zero scale i out (ma) 0 v out (v) 5.04.5 1.0 1.5 2.0 2.5 3.0 3.5 4.00.5 0 1 7 8 9 6 5 4 3 2635 g25 10 2 5v sourcing 3v (ltc2635-l) sourcing 3v (ltc2635-l) sinking 5v sinking 200s/div v cc 2v/div v out 0.5v/div 2635 g27 ltc2635-h ltc2635-l exiting power-down for hi-z option 5s/div v out 0.5v/div scl 5v/div 2635 g26 9th clock of 3rd data byte ltc2635-h dacs a-c in power-down mode v cc = 5v internal reference logic voltage (v) 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1 2 3 4 5 i cc (ma) 2635 g28 sweep sda, scl between 0v and v cc v cc = 5v v cc = 3v (ltc2635-l) 2s/div ltc2635-lmo, v cc = 3v dac output driven by 1v source through 15k resistor v out 500mv/div scl 5v/div 2635 g29 high-impedance (power-down) mode dac output set to mid-scale 9th clock of 3rd data byte 2s/div v out 5mv/div scl 5v/div 2635 g23 9th clock of 3rd data byte ltc2635-h12, v cc = 5v 3nv s typ ltc2635-l12, v cc = 3v 2.1nv s typ downloaded from: http:///
ltc2635 16 2635fb typical performance characteristics mulitplying bandwidth noise voltage vs frequency gain error vs reference input 0.1hz to 10hz voltage noise dac-to-dac crosstalk (dynamic) gain error vs temperature ltc2635 t a = 25c, unless otherwise noted. frequency (hz) db 2635 g31 20 C16 C14 C12 C10 C8 C6 C4 C2 C18 1k 100k 1m 10k v cc = 5v v ref(dc) = 2v v ref(ac) = 0.2v p-p code = full-scale frequency (hz) 100 noise voltage (nv / hz ) 500400 300 200 100 0 1k 100k 2634 g32 1m 10k v cc = 5v code = mid-scaleinternal ref ltc2635-h ltc2635-l reference voltage (v) 1 gain error (%fsr) 1.00.8 0.6 0.4 C0.6C0.8 C0.4 C0.2 0.2 0 C1.0 1.5 5 4.5 4 2635 g33 5.5 2 2.5 3 3.5 v cc = 5.5v gain error of 4 channels 1s/div 10v/div 2635 g34 v cc = 5v, v fs = 2.5v code = mid-scaleinternal ref temperature (c) C50 gain error (%fsr) 1.00.5 0 C0.5C1.0 C25 125 100 75 50 25 2635 g36 150 0 2s/div 1 dac switch 0-fs 2v/div v out 2mv/div scl 5v/div 2635 g35 9th clock of 3rd data byte ltc2635-h12, v cc = 5v 3nv s typical c ref = 0.1f downloaded from: http:///
ltc2635 17 2635fb pin functions v cc (pin 1/pin 16): supply voltage input. 2.7v v cc 5.5v (ltc2635-l) or 4.5v v cc 5.5v (ltc2635-h). bypass to gnd with a 0.1f capacitor. v outa to v outd (pins 2, 3, 8, 9/pins 1, 2, 11, 12): dac analog voltage outputs. ldac (pin 3, qfn only): asynchronous dac update. a falling edge on this input after four bytes (slave address byte plus three data bytes) have been written into the part immediately updates the dac registers with the contents of the input registers (similar to a software update). a low on this input without a complete 32-bit (four bytes including the slave address) data write transfer to the part does not update the dac output. a low on the ldac pin powers up the dacs. a software power down command is ignored if ldac is low. ca0 (pin 4/pin 4): chip address bit 0. tie this pin to v cc , gnd or leave it loating to select an i 2 c slave address for the part (see tables 1 and 2). scl (pin 5/pin 5): serial clock input pin. data is shifted into the sda pin at the rising edges of the clock. this high-impedance pin requires a pull-up resistor or current source to v cc . sda (pin 6/pin 8): serial data bidirectional pin. data is shifted into the sda pin and acknowledged by the sda pin. this pin is high impedance while data is shifted in. open drain n-channel output during acknowledgment. sda requires a pull-up resistor or current source to v cc . ref (pin 7/pin 10): reference voltage input or output. when external reference mode is selected, ref is an input (1v v ref v cc ) where the voltage supplied sets the full-scale dac output voltage. when internal ref erence is selected, the 10ppm/c 1.25v (ltc2635-l) or 2.048v (ltc2635-h) internal reference (half full-scale) is avail able at the pin. this output may be bypassed to gnd with up to 10f, and must be buffered when driving an external dc load current. dnc (pins 6, 15, qfn only): do not connect these pins. ca2 (pin 7, qfn only): chip address bit 2. tie this pin to v cc , gnd or leave it loating to select an i 2 c slave address for the part (see table 1). ca1 (pin 9, qfn only): chip address bit 1. tie this pin to v cc , gnd or leave it loating to select an i 2 c slave address for the part (see table 1). gnd (pin 10, exposed pad pin 11/pin 14, exposed pad pin 17): ground. must be soldered to pcb ground. reflo (pin 13, qfn only): reference low pin. the volt- age at this pin sets the zero-scale voltage of all dacs. this pin must be tied to gnd. (msop/qfn) downloaded from: http:///
ltc2635 18 2635fb block diagram register register register register dac a v outa (reflo) ( ldac ) ca0 (ca1) (ca2) ( ) qfn package only gndv outb v ref dac d register register register register dac b dac c v ref v outd ref v cc v ref v outc switch internal reference i 2 c interface decode i 2 c address decode power-on reset scl sda 2635 bd downloaded from: http:///
ltc2635 19 2635fb test circuits timing diagrams 2635 tc01 100 v ih(ca n ) /v il(ca n ) ca n 2635 tc02 r inh /r inl /r inf v dd gnd ca n all voltage levels refer to v ih(min) and v il(max) levels sda t low t hd(sta) t su(sta) 2635 f01 t su(sto) t hd(dat) t su(dat) t high t f t r t r t hd(sta) t sp t buf t r scl s sr p s test circuit 1 test circuit 2 figure 1. i 2 c timing test circuits for i 2 c digital i/o (see electrical characteristics) downloaded from: http:///
ltc2635 20 2635fb 9th clock of 3rd data byte 2635 f02b t 1 scl ldac figure 2a. typical ltc2635 write transaction figure 2b. ltc2635 ldac timing (qfn package only) timing diagrams c3 c2 c1 c0 a3 a2 a1 a0 ack ack ack ack a0 w a1 a2 a3 a4 a5 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 a6 start slave address 1st data byte 2nd data byte 3rd data byte sda scl ldac 2635 f02a x x x x t 1 t 2 downloaded from: http:///
ltc2635 21 2635fb operation the ltc2635 is a family of quad voltage output dacs in 16-pin qfn and 10-lead msop packages. each dac can operate rail-to-rail using an external reference, or with it s full-scale voltage set by an integrated reference. eighteen combinations of accuracy (12-, 10-, and 8-bit), power-on reset value (zero-scale, mid-scale in internal reference mode, or mid-scale in external reference mode), dac power-down output load (high impedance or 200k), and full-scale voltage (2.5v or 4.096v) are available. the ltc2635 is controlled using a 2-wire i 2 c interface. power-on reset the ltc2635-hz/-lz clear the output to zero-scale when power is irst applied, making system initialization con- sistent and repeatable. for some applications, downstream circuits are active during dac power-up, and may be sensitive to nonzero outputs from the dac during this time. the ltc2635 contains circuitry to reduce the power-on glitch: the analog output typically rises less than 5mv above zero- scale during power on. in general, the glitch amplitude decreases as the power supply ramp time is increased. see power-on reset glitch in the typical performance characteristics section. the ltc2635-hmi/-lmi/-lmx provide an alternative reset, setting the output to mid-scale when power is irst applied. the ltc2635-lmi and ltc2635-hmi power up in internal reference mode, with the output set to a mid-scale voltage of 1.25v and 2.048v, respectively. the ltc2635-lmx power-up in external reference mode, with the output set to mid-scale of the external reference. the ltc2635-lmo powers up in internal reference mode with all the dac channels placed in the high-impedance state (powered-down). input and dac registers are set to the mid-scale code, and only the internal reference is powered up, causing supply current to be typically 100a upon power up. default reference mode selection is described in the reference modes section. power supply sequencing the voltage at ref (pin 10 C qfn, pin 7 C msop) must be kept within the range C0.3v v ref v cc + 0.3v (see absolute maximum ratings). particular care should be taken to observe these limits during power supply turn- on and turn-off sequences, when the voltage at v cc is in transition. transfer function the digital-to-analog transfer function is v out(ideal) = k 2 n ?? ? ?? ? v ref ? v reflo ( ) + v reflo where k is the decimal equivalent of the binary dac input code, n is the resolution, and v ref is either 2.5v (ltc2635- lmi/-lmx/-lmo/-lz) or 4.096v (ltc2635-hmi/-hz) when in internal reference mode, and the voltage at ref when in external reference mode. i 2 c serial interface the ltc2635 communicates with a host using the stan- dard 2-wire i 2 c interface. the timing diagrams (figures 1 and 2) show the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources are required on these lines. the value of these pull-up resistors is dependent on the power supply and can be obtained from the i 2 c speciications. for an i 2 c bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pf. the ltc2635 is a receive-only (slave) device. the master can write to the ltc2635. the ltc2635 will not acknowl- edge (nak) a read request from the master. start (s) and stop (p) conditions when the bus is not in use, both scl and sda must be high. a bus master signals the beginning of a communica- tion to a slave device by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. when the master has inished communicating with the slave, it issues a stop condition. a stop condition is generated by transitioning sda from low to high while scl is high. the bus is then free for communication with another i 2 c device. downloaded from: http:///
ltc2635 22 2635fb operation acknowledge the acknowledge (ack) signal is used for handshaking between the master and the slave. an ack (active low) generated by the slave lets the master know that the lat- est byte of information was properly received. the ack related clock pulse is generated by the master. the master releases the sda line (high) during the ack clock pulse. the slave-receiver must pull down the sda bus line dur- ing the ack clock pulse so that it remains a stable low during the high period of this clock pulse. the ltc2635 responds to a write by a master in this manner but does not acknowledge a read operation; in that case, sda is retained high during the period of the ack clock pulse. chip address the state of pins ca0, ca1 and ca2 (ca1 and ca2 are only available on the qfn package) determines the slave address of the part. these pins can be each set to any one of three states: v cc , gnd or loat. this results in 27 (qfn package) or 3 (msop package) selectable addresses for the part. the slave address assignments are shown in tables 1 and 2. in addition to the address selected by the address pins, the part also responds to a global address. this address allows a common write to all ltc2635 parts to be ac- complished using one 3-byte write transaction on the i 2 c bus. the global address, listed at the end of tables 1 and 2, is a 7-bit hardwired address not selectable by ca0, ca1 or ca2. if another address is required, please consult the factory. the maximum capacitive load allowed on the address pins (ca0, ca1 and ca2) is 10pf, as these pins are driven during address detection to determine if they are loating. table 1. slave address map (qfn package) ca2 ca1 ca0 a6 a5 a4 a3 a2 a1 a0 gnd gnd gnd 0 0 1 0 0 0 0 gnd gnd float 0 0 1 0 0 0 1 gnd gnd v cc 0 0 1 0 0 1 0 gnd float gnd 0 0 1 0 0 1 1 gnd float float 0 1 0 0 0 0 0 gnd float v cc 0 1 0 0 0 0 1 gnd v cc gnd 0 1 0 0 0 1 0 gnd v cc float 0 1 0 0 0 1 1 gnd v cc v cc 0 1 1 0 0 0 0 float gnd gnd 0 1 1 0 0 0 1 float gnd float 0 1 1 0 0 1 0 float gnd v cc 0 1 1 0 0 1 1 float float gnd 1 0 0 0 0 0 0 float float float 1 0 0 0 0 0 1 float float v cc 1 0 0 0 0 1 0 float v cc gnd 1 0 0 0 0 1 1 float v cc float 1 0 1 0 0 0 0 float v cc v cc 1 0 1 0 0 0 1 v cc gnd gnd 1 0 1 0 0 1 0 v cc gnd float 1 0 1 0 0 1 1 v cc gnd v cc 1 1 0 0 0 0 0 v cc float gnd 1 1 0 0 0 0 1 v cc float float 1 1 0 0 0 1 0 v cc float v cc 1 1 0 0 0 1 1 v cc v cc gnd 1 1 1 0 0 0 0 v cc v cc float 1 1 1 0 0 0 1 v cc v cc v cc 1 1 1 0 0 1 0 global address 1 1 1 0 0 1 1 table 2. slave address map (msop package) ca0 a6 a5 a4 a3 a2 a1 a0 gnd 0 0 1 0 0 0 0 float 0 0 1 0 0 0 1 v cc 0 0 1 0 0 1 0 global address 1 1 1 0 0 1 1 downloaded from: http:///
ltc2635 23 2635fb operation write word protocol the master initiates communication with the ltc2635 with a start condition and a 7-bit slave address followed by the write bit ( w ) = 0. the ltc2635 acknowledges by pulling the sda pin low at the 9th clock if the 7-bit slave address matches the address of the part (set by ca0, ca1 or ca2) or the global address. the master then transmits three bytes of data. the ltc2635 acknowledges each byte of data by pulling the sda line low at the 9th clock of each data byte transmission. after receiving three complete bytes of data, the ltc2635 executes the command speci- ied in the 24-bit input word. if more than three data bytes are transmitted after a valid 7-bit slave address, the ltc2635 does not acknowledge (nak) the extra bytes of data (sda is high during the 9th clock). the format of the three data bytes is shown in figure 3. the irst byte of the input word consists of the 4-bit command, followed by the 4-bit dac address. the next two bytes contain the 16-bit data word, which consists of the 12-, 10- or 8-bit input code, msb to lsb, followed by 4, 6 or 8 dont-care bits (ltc2635-12, -10 and -8, respectively). a typical ltc2635 write transaction is shown in figure 4. the command bit assignments (c3-c0) and address (a3- a0) assignments are shown in tables 3 and 4. the irst four commands in the table consist of write and update operations. a write operation loads a 16-bit data word from the 32-bit shift register into the input register. in an update operation, the data word is copied from the input register to the dac register. once copied into the dac register, the data word becomes the active 12-, 10-, or 8-bit input code, and is converted to an analog voltage at the dac output. write to and update combines the irst two commands. the update operation also powers up the dac if it had been in power-down mode. the data path and registers are shown in the block diagram. table 3. command codes command* c3 c2 c1 c0 0 0 0 0 write to input register n 0 0 0 1 update (power up) dac register n 0 0 1 0 write to input register n, update (power up) all 0 0 1 1 write to and update (power up) dac register n 0 1 0 0 power down n 0 1 0 1 power down chip (all dacs and reference) 0 1 1 0 select internal reference (power up reference) 0 1 1 1 select external reference (power down internal reference) 1 1 1 1 no operation *command codes not shown are reserved and should not be used. table 4. address codes address (n)* a3 a2 a1 a0 0 0 0 0 dac a 0 0 0 1 dac b 0 0 1 0 dac c 0 0 1 1 dac d 1 1 1 1 all dacs * address codes not shown are reserved and should not be used. reference modes for applications where an accurate external reference is either not available, or not desirable due to limited space, the ltc2635 has a user-selectable, integrated reference. the integrated reference voltage is internally ampliied by 2x to provide the full-scale dac output voltage range. the ltc2635-lmi/-lmx/-lmo/-lz provides a full-scale outpu t of 2.5v. the ltc2635-hmi/-hz provides a full-scale ou tput of 4.096v. the internal reference can be useful in applica- tions where the supply voltage is poorly regulated. internal reference mode can be selected by using command 0110 b, and is the power-on default for ltc2635-hz/-lz, as well as for ltc2635-hmi/-lmi/-lmo. downloaded from: http:///
ltc2635 24 2635fb operation the 10ppm/c, 1.25v (ltc2635-lmi/-lmx/-lmo/-lz) or 2.048v (ltc2635-hmi/-hz) internal reference is available at the ref pin. adding bypass capacitance to the ref pin will improve noise performance; and up to 10f can be driven without oscillation. this output must be buffered when driving an external dc load current. alternatively, the dac can operate in external reference mode using command 0111b. in this mode, an input vo ltage supplied externally to the ref pin provides the reference (1v v ref v cc ) and the supply current is reduced. the external reference voltage supplied sets the full-scale dac output voltage. external reference mode is the power-on default for ltc2635-lmx. the reference mode of ltc2635-hz/-lz/-hmi/-lmi/-lmo (internal reference power-on default), can be changed by software command after power up. the same is true for ltc2635-lmx (external reference power-on default). power-down mode for power-constrained applications, power-down mode can be used to reduce the supply current whenever less than four dac outputs are needed. when in power-down, the buffer ampliiers, bias circuits, and integrated reference circuits are disabled, and draw essentially zero current. the dac ampliier outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 200k resistors (ltc2635-lmi/-lmx/ -lz/-hmi/-hz). for the ltc2635-lmo options, the out- put pins are not passively pulled to ground, but are also placed in a high-impedance state (open-circuited state) during power-down, typically drawing less than 0.1a. the ltc2635-lmo options power-up with all dac outputs in this high-impedance state. they remain that way until given a software or hardware update command. for all ltc2635 options, input- and dac-register contents are not disturbed during power-down. c3 input word (ltc2635-12) 1st data byte 2nd data byte 3rd data byte c2 c1 c0 a3 a2 a1 a0 d9 d10 d11 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x 1st data byte 2nd data byte 3rd data byte 1st data byte 2nd data byte 3rd data byte s write word protocol for ltc2635 input word slave address ack ack ack w 1st data byte 2nd data byte 3rd data byte ack p c3 input word (ltc2635-10) c2 c1 c0 a3 a2 a1 a0 d7 d8 d9 d6 d5 d4 d3 d2 d1 d0 x x x x x x c3 input word (ltc2635-8) c2 c1 c0 a3 a2 a1 a0 d5 d6 d7 d4 d3 d2 d1 d0 x x x x x x x x 2635 f03 figure 3. command and data input format downloaded from: http:///
ltc2635 25 2635fb operation any channel or combination of channels can be put into power-down mode by using command 0100b in combi- nation with the appropriate dac address, (n). the supply current is reduced approximately 20% for each dac powered down. the integrated reference is automatically powered down when external reference is selected using command 0111b. in addition, all the dac channels and the integrated reference together can be put into power-down mode using power down chip command 0101b. when the integrated reference is in power-down mode, the ref pin becomes high impedance (typically > 1g). for all power- down commands the 16-bit data word is ignored. normal operation resumes after executing any command that includes a dac update, (as shown in table 1) or pull- ing the asynchronous ldac pin low (qfn package only). the selected dac is powered up as its voltage output is updated. when a dac which is in a powered-down state is powered up and updated, normal settling is delayed. if less than four dacs are in a powered-down state prior to the update command, the power-up delay time is 10s. however, if all four dacs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the dac ampliiers and reference buffers. in this case, the po wer up delay time is 12s. the power-up of the integrated refer- ence depends on the command that powered it down. if the reference is powered down using the select external reference command (0111b), then it can only be powered back up using select internal reference command (0110b ). however, if the reference was powered down using power down chip command (0101b), then in addition to select internal reference command (0110b), any command (in software or using the ldac pin) that powers up the dacs will also power up the integrated reference. voltage output the ltc2635s integrated rail-to-rail ampliier has guar- anteed load regulation when sourcing or sinking up to 10ma at 5v, and 5ma at 3v. load regulation is a measure of the ampliiers ability to maintain the rated voltage accuracy over a wide range of load current. the measured change in output voltage per change in forced load current is expressed in lsb/ma. dc output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from lsb/ma to . the ampliiers dc output impedance is 0.1 when driving a load well away from the rails. when drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50 typical channel resistance of the output devices (e.g., when sinking 1ma, the minimum output voltage is 50 1ma, or 50mv). see the graph headroom at rails vs. output current in the typical performance charac- teristics section. the ampliier is stable driving capacitive loads of up to 500pf. rail-to-rail output considerations in any rail-to-rail voltage output device, the output is lim- ited to voltages within the supply range. since the analog output of the dac cannot go below gro und, it may limit for the lowest codes as shown in figure 5b. similarly, limiting can occur near full-scale when the ref pin is tied to v cc . if v ref = v cc and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc , as shown in figure 5c. no full-scale limiting can occur if v ref is less than v cc C fse. offset and linearity are deined and tested over the region of the dac transfer function where no output limiting can occur. board layout the pc board should have separate areas for the analo g and digital sections of the circuit. a single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. this keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the analog section of the ground plane. the resistance from the ltc2635 gnd pin to the ground plane should be as low as possible. resistance here will add directly to the effective dc output impedance of the device (typically 0.1). note that the ltc2635 is no more susceptible to downloaded from: http:///
ltc2635 26 2635fb operation this effect than any other parts of this type; on the con- trary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. another technique for minimizing errors is to use a sepa- rate power ground return trace on another board layer. the trace should run between the point where the power supply is connected to the board and the dac ground pin. thus the dac ground pin becomes the common point for analog ground, digital ground, and power ground. when the ltc2635 is sinking large currents, this current lows out the ground pin and directly to the power ground trace without affecting the analog ground plane voltage. it is sometimes necessary to interrupt the ground plane to conine digital ground currents to the digital portion of the plane. when doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap. c3 c2 c1 c0 a3 a2 a1 a0 c3 ww c2 command/address slave address ms data ls data c1 c0 a3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 ack ack ack ack d2 d1 d0 x x x x a0 a1 a2 a3 a4 a5 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 a6 a0 a1 a2 a3 a4 a5 a6 start stop full-scale voltage zero-scale voltage sda scl v out x = dont care 2635 f04 figure 4. typical ltc2635 input waveform?programming dac output for fu ll-scale downloaded from: http:///
ltc2635 27 2635fb figure 5. effects of rail-to-rail on a dac transfer curve (shown for 12 bits). (a) overall transfer function (b) effect of negative offset for codes near zero (c) effect of positive full-scale error for codes near full-scale 2635 f05 input code (b) (a) (c) output voltage negative offset 0v 2,048 0 0v 4,095 input code output voltage v ref = v cc v ref = v cc input code outputvoltage positivefse operation downloaded from: http:///
ltc2635 28 2635fb voltage margining application with ltc3850 (1.2v 5%) ?ltc2635? lmo o ption only application information 2635 ta02 0.1f 5v ref 72 3 4 5 to i 2 c bus 2635 ta02 6 v cc caoscl sda gnd ltc2635cmse-lmoi2 dac adac b dac d dac c 19 10k 15k 0.22f 10 8 boost1 tg1 sw1 bg1 pgnd sense + run1 sense C v fb1 pgood intv cc 1010 1nf 2.2h 0.008 v in 6.5v to 14v v out 1.2v 5% mode/pllin 500khz freqtk/ss1 i lim v in 2.2 100k i th1 10k ltc3850euf 1nf 3.32k 1nf 100pf 10k 10nf 0.1f 0.1f 0.1f sgnd 20k 4.7f 15pf 63.4k dac d v out output dac code 1.26v 0.5v 819 1.2v 0.8v 1311 1.14v 1.1v 1802 downloaded from: http:///
ltc2635 29 2635fb package description ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1691) 3.00 0.10 (4 sides) recommended solder pad pitch and dimensions 1.45 0.05 (4 sides) note:1. drawing conforms to jedec package outline mo-220 variation (weed-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1top mark (note 6) 0.40 0.10 bottom viewexposed pad 1.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 1 pin 1 notch r = 0.20 typor 0.25 45 chamfer 15 16 2 0.50 bsc 0.200 ref 2.10 0.05 3.50 0.05 0.70 0.05 0.00 C 0.05 (ud16) qfn 0904 0.25 0.05 0.50 bsc package outline downloaded from: http:///
ltc2635 30 2635fb package description mse package 10-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1664 rev d) msop (mse) 0210 rev d 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ? 0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note:1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does not include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 1.68 0.102 (.066 .004) 1.88 0.102 (.074 .004) 0.50 (.0197) bsc bottom view of exposed pad option 1.68 (.066) 1.88 (.074) 0.1016 0.0508 (.004 .002) detail b detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29ref downloaded from: http:///
ltc2635 31 2635fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as de scribed herein will not infringe on existing patent rights. revision history rev date description page number a 12/09 revise qfn pin names minor text edit in operations section 2, 17 21, 24 b 06/10 revised note 3 in the electrical characteristics section added typical application drawing and revised related parts list 1132 downloaded from: http:///
ltc2635 32 2635fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ?? linear technology corporation 2009 lt 0610 rev b ? printed in usa related parts voltage margining application with ltc3850 (1.2v 5%) ?ltc2635? lmo o ption only typical application 2635 ta02 0.1f 5v ref 72 3 4 5 to i 2 c bus 2635 ta03 6 v cc caoscl sda gnd ltc2635cmse-lmoi2 dac adac b dac d dac c 19 10k 15k 0.22f 10 8 boost1 tg1 sw1 bg1 pgnd sense + run1 sense C v fb1 pgood intv cc 1010 1nf 2.2h 0.008 v in 6.5v to 14v v out 1.2v 5% mode/pllin 500khz freqtk/ss1 i lim v in 2.2 100k i th1 10k ltc3850euf 1nf 3.32k 1nf 100pf 10k 10nf 0.1f 0.1f 0.1f sgnd 20k 4.7f 15pf 63.4k dac d v out output dac code 1.26v 0.5v 819 1.2v 0.8v 1311 1.14v 1.1v 1802 part number description comments ltc2654/ltc2655 quad 16-/12 bit, spi/i 2 c v out dacs with 10ppm/c maximum reference 4lsb inl maximum at 16 bits and 2mv offset error, rail-to-rail output, 20-lead 4mm 4mm qfn and 16-lead narrow ssop packages ltc2609/ltc2619/ ltc2629 quad 16-/14-/12-bit v out dacs with i 2 c interface 250a per dac, 2.7v to 5.5v supply range, rail-to-rail output with separate v ref pins for each dac ltc2604/ltc2614/ ltc2624 quad 16-/14-/12-bit, spi v out dacs with external reference 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, 16-lead ssop package ltc2634 quad 12-/10-/8-bit spi v out dacs with 10ppm/c reference 125a per dac, 2.7v to 5.5v supply range, 10ppm/c reference, external ref mode, rail-to-rail output, 16-pin 3mm 3mm qfn and 10-lead msop packages ltc2656/ltc2657 octal 16-/12 bit, spi/i 2 c v out dacs with 10ppm/c maximum reference 4lsb inl maximum at 16 bits and 2mv offset error, rail-to-rail output, 20-lead 4mm 5mm qfn and 16-lead tssop packages ltc2636/ltc2637 octal 12-/10-/8-bit, spi/i 2 c v out dacs with 10ppm/c reference 125a per dac, 2.7v to 5.5v supply range, 10ppm/c reference, external ref mode, rail-to-rail output, 14-lead 4mm 3mm dfn and 16-lead msop packages ltc2630/ltc2631 single 12-/10-/8-bit, spi/ i 2 c v out dacs with 10ppm/c reference 180a per dac, 2.7v to 5.5v supply range, 10ppm/c reference, rail-to-rail output, sc70 (ltc2630)/thinsot? (ltc2631) packages ltc2640 single 12-/10-/8-bit, spi v out dacs with 10ppm/c reference 180a per dac, 2.7v to 5.5v supply range, 10ppm/c reference, external ref mode, rail-to-rail output, thinsot package ltc1664 quad 10-bit, serial v out dac v cc = 2.7v to 5.5v, micropower, rail-to-rail output, 16-pin narrow ssop downloaded from: http:///

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